Improving HTM Scaling with Consistency-Oblivious Programming

We implemented two data structures in a consistency-oblivious programming (COP) style: a red black tree and a dynamic cacheoblivious B-tree. Unlike a naive transactional style, in which an operation such as an insertion is enclosed in a hardware transaction, in a COP-style there are two phases: an oblivious phase that runs with no transactions or locking, and an atomic phase that simply verifies that the oblivious phase operated correctly. If the verification fails, we retry, and then fallback to performing the transaction while holding a lock. We used the Intel hardware transactional memory instructions to implement the atomic phase. We found that the COP approach provides a performance improvement of more than a factor of five over a naive HTM transaction for high threadcount read-only workloads, and a factor of four for high threadcount read/write workloads. To achieve good performance when using HTM, one must distinguish between failures that are likely to succeed upon retry (for example, a conflict on the lock) from failures that indicate real conflicts (such as two threads both modifying the data structure).